1. Field of the Invention
The present invention relates to multiple processor computer architectures. More particularly, the present invention relates to a multiple processor architecture for dynamic steering of undirected system interrupts to a particular processor.
2. Art Background
In most computer systems, it is desirable and necessary to enable the processor to respond to device signals and conditions which arise during the operation of the computer system. Such signals and conditions may arise as a result of anticipated signal inputs from a variety of internal and external devices, or may arise as a result of an unexpected event or occurrence of condition. When an event or condition occurs which bears upon computer system operation, the source of such event or condition will issue an interrupt to the processor requesting that the event or condition be acknowledged and serviced. Because a number of devices may interact with the processor, a priority allocation scheme is necessary in order to permit the processor to respond to the appropriate interrupt in the proper order.
Many methods and architectures exist for directing interrupts in uniprocessor computer systems. In a single processor computer system, all interrupts are necessarily serviced by the single processor, the only constraint being the order in which the interrupts are serviced. Most frequently, interrupts are assigned a priority, and are serviced in either ascending or descending order. In more complex multiple processor computer systems, interrupt servicing may be described in terms of symmetric and asymmetric interrupt servicing conventions. In an asymmetric multiple processor computer system, all interrupts are centralized and are all directed to one particular processor chosen to handle interrupt service requests. In symmetric multiple processor systems on the other hand, interrupts may be directed to any processor, depending on computer system needs and tasks currently being executed by processors within the multiple processing architecture.
Interrupts may take one of three forms. There may be directed interrupts, which are sent to a particular processor by the requesting device. Directed interrupts may be either "hard", wherein the interrupts are issued by specific devices generating a hardware signal, or "soft", wherein the interrupt is generated by a particular processor and directed to another processor under software control. Because the requesting device has specified a processor which is to service the interrupt request, no decision is necessary where to direct the interrupt.
A second type of interrupt is the broadcast interrupt, which, when it occurs, is of consequence to every device operating within the computer system. Because broadcast interrupts potentially affect every device within the computer system, broadcast interrupts are issued to, and received by, every device within the computer. An example requiring a broadcast interrupt is a hardware failure such as a power supply failure, wherein it is desired to alert all devices in the computer system that a power fail condition will occur momentarily. Because both directed interrupts and broadcast interrupts do not require the determination of a particular processor for servicing the interrupt, there exist numerous architectures allocating the directed or broadcast interrupts to one or all of the several processors operating within the multiple processor computer system.
The third type of interrupt, the undirected interrupt, is the most frequently encountered interrupt in multiple processor computer systems. Undirected interrupts may be received from any of a wide variety of computer system devices, including disk controllers, tape controllers, serial and parallel I/O ports, and any other device which may be equally shared by any processor within the computer system. Prior art multiple processor architectures frequently assign a particular processor to service all of the undirected interrupts issued by system components and peripherals. A detraction of dedicating a single processor to service only undirected interrupt service requests is that such processor is not available for other general purpose processing. In particular, during periods of low or minimal interdevice communication but intensive numeric computation, a dedicated interrupt service processor could not participate in the numeric computation, and thereby could not improve overall computer system performance. Alternatively, prior art interrupt service routines intended for multiple processor architectures may force the undirected interrupt service request upon the first available processor, without regard to the task the processor is executing, or which interrupts may be most expediously processed.
As will be discussed below, the present invention provides methods and apparatus for dynamically allocating undirected interrupt service requests to any one of several processors present in the multiple processor architecture by implementing an interrupt target register which points the interrupt service request to a particular processor. Moreover, the present invention permits review of all pending undirected interrupts prior to allocation to a particular processor. It is therefore possible to assign undirected interrupt service requests to a processor which may be concurrently servicing an interrupt of similar priority. Flexible and dynamic assignment of undirected interrupt service requests to processors results in a more effective interrupt servicing mechanism, thereby improving overall system performance.